1. Field of the Invention
The present invention relates to the process of transferring data between integrated circuits. More specifically, the present invention relates to a method and an apparatus for aligning capacitive transmitter pads on a first chip with capacitive receiver pads on a second chip in a manner that can tolerate variations in alignment between the first chip and the second chip.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is beginning to create a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines within a printed circuit board.
However, it is not a simple matter to align the chips properly. One possible alignment technique is to mechanically align the chips during the assembly process and to then bond the chips together with an adhesive. Unfortunately, permanently bonding incompletely tested chips can give rise to the multi-chip-module (MCM) problem, in which a bad $5 chip can ruin a $1000 MCM. In order to allow chips to be replaced they cannot be firmly attached to each other.
What is needed is a method and an apparatus for aligning capacitive transmitter pads on a first chip with capacitive receiver pads on a second chip in a manner that can tolerate variations in alignment between the first chip and the second chip.
Note that the simplest method to tolerate misalignments is to make the transmitter pads and/or receiver pads larger, but this reduces the number of pads that can be integrated into a given semiconductor chip and thereby decreases inter-chip communication bandwidth.
One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
In a variation on this embodiment, there are a greater number of smaller transmitter pads than receiver pads so that multiple transmitter pads can drive a single receiver pad. In this variation, multiple transmitter pads under a single receiver pad are driven with the same signal.
In a variation on this embodiment, driving the multiple transmitter pads with the same signal additionally involves driving adjacent transmitter pads with an inverse signal to provide return current.
In a variation on this embodiment, the transmitter pads collectively cover more area than the receiver pads so that the receiver pads remain proximate to transmitter pads in spite of alignment variations between the first chip and the second chip.
In a variation on this embodiment, the transmitter pads are located in the highest metal layer of the first chip, and the receiver pads are located in the highest metal layer of the second chip.
In a variation on this embodiment, the transmitter pads are covered by an overglass layer on the first chip, and the receiver pads are covered by an overglass layer on the second chip.
In a variation on this embodiment, selectively routing the data signals to transmitter pads involves using a multiplexing array to selectively route the data signals.
In a variation on this embodiment, the alignment process takes place either periodically or continuously.
In a variation on this embodiment, the transmitter pads are arranged in a two-dimensional array on the first chip, and the receiver pads are arranged in a two-dimensional array on the second chip.
In a variation on this embodiment, the receiver pads and transmitter pads are square.
In a variation on this embodiment, the receiver pads and the transmitter pads are not square.
Note that the above-described techniques relax the need for precise mechanical alignment and allows the two chips to move relative to each other during operation. As such, chips situated face-to-face do not require an adhesive bond. Hence, this technique facilitates easy removal and replacement of bad chips, thereby reducing the requirement for known good chips and improving overall assembly yield.